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X5083
CPU Supervisor with 8Kbit SPI EEPROM
FEATURES * Low VCC detection and reset assertion --Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V --Re-program low VCC reset threshold voltage using special programming sequence. --Reset signal valid to VCC = 1V * Selectable time out watchdog timer * Long battery life with low power consumption --<50A max standby current, watchdog on --<1A max standby current, watchdog off --<400A max active current during read * 8Kbits of EEPROM * Save critical data with Block LockTM memory --Block lock first or last page, any 1/4 or lower 1/2 of EEPROM array * Built-in inadvertent write protection --Write enable latch --Write protect pin * SPI Interface - 3.3MHz clock rate * Minimize programming time --16 byte page write mode --5ms write cycle time (typical) * SPI modes (0,0 & 1,1) * Available packages --8-lead TSSOP, 8-lead SOIC, 8-Lead PDIP BLOCK DIAGRAM
POR and Low Voltage Reset Generation Reset & Watchdog Timebase Watchdog Transition Detector Watchdog Timer Reset
APPLICATIONS * Communications Equipment --Routers, Hubs, Switches --Set Top Boxes * Industrial Systems --Process Control --Intelligent Instrumentation * Computer Systems --Desktop Computers --Network Servers * Battery Powered Equipment
Typical Application
2.7-5.0V
VCC VCC
uC
X5083
RESET CS SCK SI SO WP VSS
10K
RESET SPI
VSS
VCC
VTRIP
+
RESET (X5083)
-
X5083
Standard VTRIP Level
4.63V (+/-2.5%) 4.38V (+/-2.5%)
Suffix
-4.5A -4.5 -2.7A -2.7
CS/WDI
SI SO SCK WP Command Decode & Control Logic Protect Logic
Status Register EEPROM Array 8Kbits
2.93V (+/-2.5%) 2.63V (+/-2.5%)
See "Ordering Information" on page 21 for more details For Custom Settings, call Xicor.
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Characteristics subject to change without notice.
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X5083
DESCRIPTION This device combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller PIN CONFIGURATION
8-Lead TSSOP RESET VCC CS/WDI SO 1 2 3 4 8 7 X5083 6 5 SCK SI VSS WP CS/WDI SO WP VSS 8-Lead SOIC, PDIP 1 8 2 7 3 X5083 6 4 5 VCC RESET SCK SI
fails to restart a timer within a selectable time out interval, the device activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET is asserted until VCC returns to the proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
PIN DESCRIPTION
Pin (SOIC/ Pin PDIP) TSSOP 1 3
Name
Function
CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET going active. SO SI Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This "Locks" the memory to protect it against inadvertent changes when WP is HIGH, the device operates normally. Ground Supply Voltage Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on power up at about 1V and remains active for 250ms after the power supply stabilizes.
2 5
4 7
6
8
SCK
3
5
WP
4 8 7
6 2 1
VSS VCC RESET
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X5083
PRINCIPLES OF OPERATION Power On Reset Application of power to the X5083 activates a power on reset circuit. This circuit goes LOW at 1V and pulls the RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. RESET active also blocks communication to the device through the SPI interface. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET, allowing the processor to begin executing code. While VCC < VTRIP communications to the device are inhibited. Low Voltage Monitoring During operation, the X5083 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition and terminates any SPI communication in progress. The RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. When VCC falls below VTRIP, any communications in progress are terminated and communications are inhibited until VCC exceeds VTRIP for tPURST. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits with no action taken by the microprocessor these bits remain unchanged, even after total power failure. VCC Threshold Reset Procedure The X5083 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5083 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 01h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP value)
WP VP = 15-18V
CS 01234567 SCK 16 Bits SI 06h WREN 02h Write 0001h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
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Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the new VTRIP voltage, apply the desired VTRIP threshold voltage to the Vcc pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 03h.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V)
WP VP = 15-18V
CS 01234567 SCK 16 Bits SI 06h WREN 02h Write 0003h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
Figure 3. Sample VTRIP Reset Circuit
4.7K VP Adjust VTRIP Adj. 1 2 3 4 X5083 8 7 6 5 RESET C
SCK SI SO CS
Run
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Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute Reset VTRIP Sequence
Set VCC = VCC Applied = Desired VTRIP
New VCC Applied = Old VCC Applied + Error
Execute Set VTRIP Sequence
New VCC Applied = Old VCC Applied - Error
Apply 5V to VCC
Execute Reset VTRIP Sequence
Decrement VCC (VCC = VCC - 50mV)
NO
RESET pin goes active? YES
Error -Emax
Measured VTRIP Desired VTRIP
Error Emax
-Emax < Error < Emax DONE Emax = Maximum Desired Error
SPI Serial Memory The memory portion of the device is a CMOS serial EEPROM array with Xicor's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the bus and asserts RESET output if the watchdog timer is enabled and there is no bus
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activity within the user selectable time out period or the supply voltage falls below a preset minimum VTRIP. The device contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.
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X5083
Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 7). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows. Status Register/Block Lock/WDT Byte 7
0
Block Lock Memory Xicor's block lock memory provides a flexible mechanism to store and lock system ID and parametric information. There are seven distinct block lock memory areas within the array which vary in size from one page to as much as half of the entire array. These areas and associated address ranges are block locked by writing the appropriate two byte block lock instruction to the device as described in Table 1 and Figure 9. Once a block lock instruction has been completed, that block lock setup is held in the nonvolatile status register until the next block lock instruction is issued. The sections of the memory array that are block locked can be read but not written until block lock is removed or changed.
6
0
5
0
4
WD1
3
WD0
2
BL2
1
BL1
0
BL0
Table 1. Instruction Set and Block Lock Protection Byte Definition Instruction Format
0000 0110 0000 0100 0000 0001
Instruction Name and Operation
WREN: set the write enable latch (write enable operation) WRDI: reset the write enable latch (write disable operation) Write status instruction--followed by: Block lock/WDT byte: (See Figure 1) --->none of the array 000WD1 WD2000 --->no block lock: 00h-00h 000WD1 WD2001 --->block lock Q1: 0000h-00FFh --->lower quadrant (Q1) 000WD1 WD2010 --->block lock Q2: 0100h-01FFh --->Q2 000WD1 WD2011 --->block lock Q3: 0200h-02FFh --->Q3 000WD1 WD2100 --->block lock Q4: 0300h-03FFh --->upper quadrant (Q4) 000WD1 WD2101 --->block lock H1: 0000h-01FFh --->lower half of the array (H1) 000WD1 WD2110 --->block lock P0: 0000h-000Fh --->lower page (P0) 000WD1 WD2111 --->block lock Pn: 03F0h-03FFh --->upper page (PN) READ STATUS: reads status register & provides write in progress status on SO pin WRITE: write operation followed by address and data READ: read operation followed by address
0000 0101 0000 0010 0000 0011
Watchdog Timer The watchdog timer bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the WRSR instruction. A change to the Watchdog Timer, either setting a new time out period or turning it off or on, takes effect, following either the next command (read or write) or cycling the power to the device. The recommended procedure for changing the Watchdog Timer settings is to do a WREN, followed by a write status register command. Then execute a software loop to read the status register until the MSB of the status byte is zero. A valid alternative is to do a
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WREN, followed by a write status register command. Then wait 10ms and do a read status command. Table 2. Watchdog Timer Definition Status Register Bits WD1
0 0 1 1
WD0
0 1 0 1
Watchdog Time Out (Typical)
1.4 seconds 600 milliseconds 200 milliseconds disabled (factory default)
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X5083
Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM array sequence (Figure 5). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 6). Write Sequence Prior to any attempt to write data into the device, the "Write Enable" Latch (WEL) must first be set by issuing the WREN instruction (Figure 7). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be "0's". The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the same page and overwrite any data that may have been previously written. For a write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 8). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 9). Data bits 5, 6 and 7 must be "0".
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Read Status Operation If there is not a nonvolatile write in progress, the read status instruction returns the block lock setting from the status register which contains the watchdog timer bits WD1, WD0, and the block lock bits IDL2-IDL0 (Figure 6). The block lock bits define the block lock condition (Table 1). The watchdog timer bits set the operation of the watchdog timer (Table 2). The other bits are reserved and will return '0' when read. See Figure 6. During an internal nonvolatile write operaiton, the Read Status Instruction returns a HIGH on SO in the first bit following the RDSR instruction (the MSB). The remaining bits in the output status byte are undefined. Repeated Read Status Instructions return the MSB as a `1' until the nonvolatile write cycle is complete. When the nonvolatile write cycle is completed, the RDSR instruction returns a `0' in the MSB position with the remaining bits of the status register undefined. Subsequent RDSR instructions return the Status Register Contents. See Figure 10. RESET Operation The RESET output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time out limit. The RESET output is an open drain output and requires a pull up resistor. Operational Notes The device powers-up in the following state: - The device is in the low power standby state. - A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. - SO pin is high impedance. - The write enable latch is reset. - Reset signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: - A WREN instruction must be issued to set the write enable latch. - CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. - When VCC is below VTRIP, communications to the device are inhibited.
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Characteristics subject to change without notice.
X5083
Figure 5. Read Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30
Read Instruction (1 Byte) SI
Byte Address (2 Byte) 15 14 3 2 1 0
Data Out
High Impedance SO
7
6
5
4
3
2
1
0
Figure 6. Read Status Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
... ...
W D 1 W D 0 B L 2 B L 1 B L 0
Read Status Instruction SI
SO
...
SO = Status Reg When no Nonvolatile Write Cycle
Figure 7. WREN/WRDI Sequence
CS
0 SCK
1
2
3
4
5
6
7
Instruction (1 Byte) SI
SO
High Impedance
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X5083
Figure 8. EEPROM Array Write Sequence
CS 0 SCK Instruction SI 16 Bit Address 15 14 13 32 Data Byte 1 5432 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
1
0
7
6
1
0
CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 432 Data Byte 3 5432 Data Byte N 4 321
SI
7
6
5
1
0
7
6
1
0
6
5
0
Figure 9. Status Register Write Sequence
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction SI 6 5 4
Data Byte 3 2 B L 2 1 B L 1 0 B L 0 WW DD 10
SO
High Impedance
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X5083
Figure 10. Read Nonvolatile Write Status
CS
01234567
01234567
SCK
READ STATUS INSTRUCTION READ STATUS INSTRUCTION
SI
NONVOLATILE WRITE IN PROGRESS
SO
SO MSB HIGH while in the Nonvolatile write cycle SO MSB still HIGH indicates Nonvolatile write cycle still in progress
CS
01234567
01234567
SCK
READ STATUS INSTRUCTION READ STATUS INSTRUCTION
SI
NONVOLATILE WRITE ENDS
43210 WD1 WD0 BL2 BL1 BL0
SO
1st detected SO MSB LOW indicates end of Nonvolatile write cycle
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X5083
Figure 11. End of Nonvolatile Write (no Polling) tWC
CS
0 SCK
1
2
3
4
5
6
7
NEXT INSTRUCTION SI
Non-volatile Write Operation
Wait tWC after a write for new operation, if not using polling procedure
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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ABSOLUTE MAXIMUM RATINGS Temperature under bias .................. -65C to +135C Storage temperature ....................... -65C to +150C Voltage on any pin with respect to VSS ......................................-1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds)........ 300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial
Min.
0C -40C
Max.
70C +85C
Voltage Option
-2.7 Blank
Limits
2.7V to 5.5V 4.5V-5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO VIL
(1) (1)
Parameter
VCC write current (active) VCC read current (active) VCC standby current WDT = OFF VCC standby current WDT = ON VCC standby current WDT = ON Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage Output HIGH voltage Reset output LOW voltage
Min.
Typ.
Max.
5 0.4 1 50 20
Unit
mA mA A A A A A V V V V V V V V
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 3.6V VIN = VSS to VCC VOUT = VSS to VCC
0.1 0.1 -0.5 VCC x 0.7
10 10 VCC x 0.3 VCC + 0.5 0.4 0.4 0.4
VIH
VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLRS
VCC > 3.3V, IOL = 2.1mA 2V < VCC 3.3V, IOL = 1mA VCC 2V, IOL = 0.5mA VCC > 3.3V, IOH = -1.0mA 2V < VCC 3.3V, IOH = -0.4mA VCC 2V, IOH = -0.25mA IOL = 1mA
VCC - 0.8 VCC - 0.4 VCC - 0.2 0.4
V
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POWER-UP TIMING Symbol
tPUR
(2) (2)
Parameter
Power-up to read operation Power-up to write operation
Min.
Max.
1 5
Unit
ms ms
tPUW
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V. Symbol
COUT CIN
(2) (2)
Test
Output capacitance (SO, RESET, RESET) Input capacitance (SCK, SI, CS, WP)
Max.
8 6
Unit
pF pF
Conditions
VOUT = 0V VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
5V 5V 3.3K
A.C. TEST CONDITIONS
Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
1.64K SO Output 1.64K 100pF RESET
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing 2.7V-5.5V Symbol
fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI tFI
(3) (3)
Parameter
Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time
Min.
0 300 150 150 130 130 20 20
Max.
3.3
Unit
MHz ns ns ns ns ns ns ns
2 2 100 10
s s ns ms
tCS tWC(4)
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X5083
Data Output Timing 2.7V-5.5V Symbol
fSCK tDIS tV tHO tRO(3) tFO
(3)
Parameter
Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time
Min.
0
Max.
3.3 150 130
Unit
MHz ns ns ns ns ns
0 50 50
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
SO
High Impedance
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X5083
Power-Up and Power-Down Timing
VCC VTRIP 0 Volts tR RESET tPURST tPURST VTRIP tF tRPD
RESET Output Timing Symbol
VTRIP
Parameter
Reset trip point voltage, X5083PT-4.5A (See note 6) Reset trip point voltage, X5083PT Reset trip point voltage, X5083PT-2.7A Reset trip point voltage, X5083PT-2.7 Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC
Min.
4.5 4.25 2.85 2.55 100 0.1 0.1 1
Typ.
4.63 4.38 2.93 2.63 200
Max.
4.75 4.5 3.00 2.7 280 500
Unit
V
tPURST tRPD tF tR
(5) (5) (5)
ms ns ns ns V
VRVALID
Note:
(5) This parameter is periodically sampled and not 100% tested. (6) PT= Package/Temperature
CS vs. RESET Timing
CS tCST RESET tWDO tRST tWDO tRST
RESET Output Timing Symbol
tWDO
Parameter
Watchdog time out period, WD1 = 1, WD0 = 1(default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS pulse width to reset the watchdog Reset time out
Min.
Typ.
OFF 200 600 1.4 200
Max.
Unit
100 450 1 400 100
300 800 2 300
ms ms sec ns ms
tCST tRST
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X5083
VTRIP Programming Timing Diagram
VCC (VTRIP)
VTRIP tTSU VP tTHD
VPE tVPS tVPH tVPO
tPCS
CS
tRP
SCK
SI 06h WREN 02h Write 0001h (set) 0003h (reset) Addr. 00 Data
VTRIP Programming Parameters Parameter
tVPS tVPH tPCS tTSU tTHD tWC tVPO tRP VP VTRAN Vtv
Description
VTRIP program enable voltage setup time VTRIP program enable voltage hold time VTRIP programming CS inactive time VTRIP setup time VTRIP hold (stable) time VTRIP write cycle time VTRIP program enable voltage off time (between successive adjustments) VTRIP program recovery period (between successive adjustments) Programming voltage VTRIP programmed voltage range VTRIP program variation after programming (0-75C). (programmed at 25C)
Min.
1 1 1 1 10
Max.
Unit
s s s s ms
10 0 10 15 2.0 -25 18 5.0 +25
ms s ms V V mV
Note 1: VTRIP programming parameters are periodically sampled and are not 100% tested. Note 2: For custom VTRIP settings, Contact Factory.
REV 1.1.6 6/25/02
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Characteristics subject to change without notice.
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X5083
PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51)
Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
0.325 (8.25) 0.300 (7.62)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
REV 1.1.6 6/25/02
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Characteristics subject to change without notice.
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X5083
PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45 0.020 (0.50)
0.050" Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" Typical
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.6 6/25/02
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Characteristics subject to change without notice.
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X5083
PACKAGING INFORMATION 8-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) (1.78) .031 (.80) .041 (1.05) See Detail "A" (0.42) (0.65) All Measurements Are Typical Seating Plane (4.16) (7.72)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.6 6/25/02
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Characteristics subject to change without notice.
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X5083
Ordering Information VCC Range
4.5-5.5V
VTRIP Range
4.5.4.75
Package
8-Pin PDIP 8L SOIC
Operating Temperature Range
0-70C 0-70C -40-85C 0-70C 0-70C -40-85C 0-70C 0-70C -40-85C 0-70C 0-0C -40-85C 0-70C
Part Number RESET (Active LOW)
X5083P-4.5A X5083S8-4.5A X5083S8I-4.5A X5083P X5083S8 X5083S8I X5083V8 X5083S8-2.7A X5083S8I-2.7A X5083V8-2.7A X5083S8-2.7 X5083S8I-2.7 X5083V8-2.7
4.5-5.5V
4.25.4.5
8-Pin PDIP 8L SOIC 8L TSSOP
2.7-5.5V
2.85-3.0
8L SOIC 8L TSSOP
2.7-5.5V
2.55-2.7
8L SOIC 8L TSSOP
Part Mark Convention 8-Lead TSSOP EYWW XXXXX 8-Lead SOIC/PDIP X5083X XX
583F = 2.7 to 5.5V, 0 to +70C, VTRIP = 2.55-2.7V 583G = 2.7 to 5.5V, -40 to +85C, VTRIP = 2.55-2.7V 583AN = 2.7 to 5.5V, 0 to +70C, VTRIP = 2.85-3.0V 583AP = 2.7 to 5.5V, -40 to +85C, VTRIP = 2.85-3.0V X583 = 4.5 to 5.5V, 0 to +70C, VTRIP = 4.25-4.5V 583I = 4.5 to 5.5V, -40 to +85C, VTRIP = 4.25-4.5V 583AL = 4.5 to 5.5V, 0 to +70C, VTRIP = 4.5-4.75V 583AM = 4.5 to 5.5V, -40 to +85C, VTRIP = 4.5-4.75V YWW = year/work week device is packaged.
F = 2.7 to 5.5V, 0 to +70C, VTRIP = 2.55-2.7V G = 2.7 to 5.5V, -40 to +85C, VTRIP = 2.55-2.7V AN = 2.7 to 5.5V, 0 to +70C, VTRIP = 2.85-3.0V AP = 2.7 to 5.5V, -40 to +85C, VTRIP = 2.85-3.0V Blank = 4.5 to 5.5V, 0 to +70C, VTRIP = 4.25-4.5V I = 4.5 to 5.5V, -40 to +85C, VTRIP = 4.25-4.5V AL = 4.5 to 5.5V, 0 to +70C, VTRIP = 4.5-4.75V AM = 4.5 to 5.5V, -40 to +85C, VTRIP = 4.5-4.75V
REV 1.1.6 6/25/02
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Characteristics subject to change without notice.
20 of 21
X5083
LIMITED WARRANTY
(c)Xicor, Inc. 2002 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice.
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